Embodiments of the inventive subject matter generally relate to the field of data processing, and, more particularly, to merging compressed data sets while maintaining compression.
Processors designed with trace capabilities capture information about a variety of aspects to aid in error analysis/validation of hardware and/or software debugging. The trace hardware captures data of various types and from various sources that can include cores, cache, a branch predictor, arithmetic logic unit, ports, buses, etc. The information is captured from this variety of sources at defined intervals (e.g., every cycle, half cycle, etc.) and stored in on-chip structures, sometimes referred to as trace arrays. This information is collected over periods of time that can span millions of cycles. The combination of fine granularity in the information and large collection periods yields a large amount of data to be captured in the trace arrays.
The data is written into the trace arrays in accordance with designated starts and stops with continuous writing in a round-robin fashion. Compression values are used limit consumption of storage space to unique non-repeating data. The trace data is read out for analysis in compressed form either periodically or responsive to requests or commands.